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Freescale公司的SGTL5000是集成了耳機放大器的低功耗立體聲CODEC,提供線路輸入,麥克風輸入,線路輸出,耳機輸出和數字I/O,是手持產品的完整的音頻解決方案.模擬輸入ADC的SNR為- 85dB,具有環繞,低音,音質控制/參數均衡/圖像均衡以及時鐘控制等,主要用在手持導航設備(PND),電子書,智能手機,平板電腦和GPS等.本文介紹了SGTL5000主要特性,方框圖, 20QFN和32QFN封裝的典型應用電路, 平板電腦方框圖以及SGTL5000評估平臺主要特性和電路圖. The SGTL5000 is a Low Power Stereo Codec with Headphone Amp from Freescale, and is designed to provide a complete audio solution for portable products needing line-in, mic-in, line-out, headphone-out, and digital I/O. Deriving it’s architecture from best in class, Freescale integrated products that are currently on the market. The SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available. Target markets include portable media players, GPS units, and smart phones. Features such as capless headphone design and an internal PLL, help lower overall system cost. SGTL5000主要特性: Analog Inputs • Stereo Line In - Support for external analog input • Stereo Line In - Codec bypass for low power • MIC bias provided (5.0 x 5.0 mm QFN, 3.0 x 3.0 mm QFN TA2) • Programmable MIC gain • ADC - 85 dB SNR (-60 dB input) and -73 dB THD+N (VDDA = 1.8 V) Analog Outputs • HP Output - Capless design • HP Output - 45 mW max into 16 ohm load @ 3.3 V • HP Output - 100 dB SNR (-60 dB input) and -80 dB THD+N (VDDA = 1.8 V, 16 ohm load, DAC to headphone) • Line Out - 100 dB SNR (-60 dB input) and -85 dB THD+N (VDDIO = 3.3 V) Digital I/O • I2S port to allow routing to Application Processor Integrated Digital Processing • Freescale Surround, Freescale Bass, tone control/ parametric equalizer/graphic equalizer Clocking/Control • PLL allows input of an 8.0 MHz to 27 MHz system clock - Standard audio clocks are derived from PLL Power Supplies • Designed to operate from 1.62 to 3.6 volts SGTL5000優勢: High performance at low power for DAC-to-HP 101 dB SNR @ < 9.3 mW Extremely low power modes 98 dB SNR @ < 4 mW Small PCB footprint 3 mm x 3 mm QFN Allows for no-cost system customization SGTL5000應用: Portable Navigation Devices eReaders Media Phones Smartphones Tablets Global Positioning System (GPS) 
圖1.SGTL5000簡化方框圖
圖2.SGTL5000簡化應用框圖
圖3.20QFN封裝的SGTL5000典型應用電路
圖4.20QFN封裝的SGTL5000最低功耗應用電路
圖5.32QFN封裝的SGTL5000最低功耗應用電路(1)
圖6.32QFN封裝的SGTL5000最低功耗應用電路(2)
圖7.平板電腦方框圖 SGTL5000評估平臺 The evaluation platform is designed to allow the user to test the features and performance of the SGTL5000 audio codec. The evaluation board can be used as a demo or development platform. SGTL5000評估平臺主要特性: • SGTL5000 Audio Codec • LINEIN RCA analog input jack • LINEOUT RCA analog output jack • Selectable mini-jack or onboard microphone input • Stereo headphone mini-jack analog output, with optional capless design circuitry • Two-row headers for buffered I2S digital input/output • Support for onboard or external MCLK source • USB to I2C/SPI communication port • 5V input voltage through either internal LDO regulators, or external individual Supplies
圖8. SGTL5000評估平臺外形圖
圖9. SGTL5000評估平臺方框圖
圖10. SGTL5000評估平臺電路圖(1)
圖11. SGTL5000評估平臺電路圖(2)
圖12. SGTL5000評估平臺電路圖(3)
圖13. SGTL5000評估平臺電路圖(4)
圖14. SGTL5000評估平臺電路圖(5)
圖15. SGTL5000評估平臺電路圖(6) 詳情請見: 
SGTL5000.pdf
(2.44 MB)
KTSGTL5000UG.pdf
(4.94 MB)
來源：網絡 |
