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Freescale公司的MPC5668x系列是Qorivva 雙核32位MCU,集成了FlexRay™,以太網和媒體本地總線. MPC5668x系列采用32位CPU核(e200z650),和Power架構(Power Architecture®)兼容,速率高達116MHz,2MB閃存,Nexus開發接口(NDI)和IEEE-ISTO 5001-2003,主要用在汽車網關和車體控制模塊和中央網關.本文介紹了MPC5668x主要特性,方框圖以及MPC5668G評估板(EVB)主要特性和詳細電路圖. Electronic content in vehicles keeps increasing. A number of different communication protocols, including consumer protocols making their way into the automotive market, keep these electronic components working together. The 32-bit Qorivva MPC5668G MCU, built on dual core Power Architecture® technology, connects all the possible communication protocols you can find in a car at one single point. The dual-core architecture provides the performance throughput needed to maintain real-time operation backed-up by a strong third-party ecosystem support. MPC5668x主要特性: • 32-bit CPU core complex (e200z650) – Compliant with Power Architecture embedded category – 32 KB unified cache with line locking and eight-entry store buffer16 – Execution speed static to 116 MHz • 32-bit I/O processor (e200z0) – Execution speed static to 1/2 CPU core speed (58 MHz) • 2 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 512 KB + 80 KB (592 KB) on-chip ECC SRAM (MPC5668G) • 128 KB on-chip ECC SRAM (MPC5668E) • 16-entry Memory Protection Unit (MPC5668E only) • Direct memory access controller – 16-channel on MPC5668G – 32-channel on MPC5668E • Fast ethernet controller – Supports 10-Mbps and 100-Mbps IEEE 802.3 MII, 10-Mbps 7-wire interface – IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) • Media Local Bus (MLB) interface (MPC5668G only) – Supports 16 logical channels, max speed 1024 Fs • Interrupt controller (INTC) supports 316 external interrupt vectors (22 are reserved) • System clocks – Frequency-modulated phase-locked loop (FMPLL) – 4 – 40 MHz crystal oscillator (XTAL) – 32 kHz crystal oscillator (XTAL) – Dedicated 16 MHz and 128 kHz internal RC oscillators • Analog to Digital Converter (ADC) module – 10-bit A/D resolution – 32 external channels – 36 internal channels (MPC5668G) – 64 internal channels (MPC5668E) • Cross-Triggering Unit (MPC5668E only) – Internal conversion triggering for ADC – Triggerable by internal timers or eMIOS200 • Deserial Serial Peripheral Interface (DSPI) – Four individual DSPI modules – Full duplex, synchronous transfers – Master or slave operation • Inter-IC communication (I2C) interface – Four individual I2C modules – Multi-master operation • Serial Communication Interface (eSCI) module – Two-channel DMA interface – Configurable as LIN bus master • eMIOS200 timed input/output – 24 channels, 16-bit timers (MPC5668G) – 32 channels, 16-bit timers (MPC5668E) • Controller Area Network (FlexCAN) module – Compliant with CAN protocol specification, Version 2.0B active – 64 mailboxes, each configurable as transmit or receive • Dual-channel FlexRay controller – Full implementation of FlexRay Protocol Specification 2.1, RevA – 128 message buffers • JTAG controller (MPC5668G only) – Compliant with the IEEE 1149.1-2001 • Nexus Development Interface (NDI) – Available in 256 MAPBGA package only – Compliant with IEEE-ISTO 5001-2003 – Nexus class 3 development support on e200z650 – Nexus class 2+ development support on e200z0 • Internal voltage regulator allows operation from single 3.3 V or 5 V supply MPC5668x目標應用: Automotive Gateways Body Control Module and Central Gateway 
圖1.MPC5668G方框圖
圖2.MPC5668E方框圖 MPC5668G評估板(EVB) This user’s manual details the setup and configuration of the Freescale Semiconductor MPC5668 Evaluation Board (hereafter referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the MPC5668 family of microprocessors, and to facilitate hardware and software development. At the time of writing this document, the MPC5668 family is offered in a 208MAPBGA package. A 256MAPBGA package supporting Nexus debug is also available for development purposes. The EVB is intended for bench / laboratory use and has been designed using normal temperature specified components (+70°C).
圖3. MPC5668G評估板(EVB)外形圖 MPC5668G評估板(EVB)主要特性: The EVB provides the following key features: • MCU Socket supporting the 208BGA production package and the 256BGA development package. • Single 12-14V external power supply input with on-board regulators to provide all of the necessary EVB and MCU voltages. Power may be supplied to the EVB via a 2.1mm barrel style power jack or a 2-way level connector. 12V operation allows in-car use if desired. • Flexible on-board power supply configuration with the option to bypass the internal MCU regulators if desired. • Master power switch and regulator status LED’s – Regulators connected to the ADC to allow monitoring. • User reset switch with reset status LED’s • User configurable Low Voltage Inhibit to monitor the status of the 3.3V and 5V regulators. • Control of the BOOTCFG status via a dedicated jumper. • Flexible MCU clocking options: _ 40MHz Oscillator Crystal _ 32Khz Watch Crystal _ SMA connector to allow external clock support _ 8Mhz Oscillator circuit. • SMA connector on MCU-CLKOUT signal for easy access. • Standard 14-pin ONCE debug connector and 38-pin MICTOR Nexus connectors. • All MCU signals are accessible on port-ordered groups of 0.1” pitch headers. • DSPI A signals can be routed to a set of shift registers to allow a 32-bit phantom port to be created. • SCI channels A and B can be routed to a standard DB9 female connector (PC RS-232 compliant) via a Maxim physical interface. • SCI channels C and D can be routed to LIN interface header (0.1”) and molex connectors, both will full physical transceivers. • FlexCAN channels A and B can be routed to 0.1” headers and DB9 connector via a Philips high speed CAN transceiver which supports both 3.3V and 5V inputs. • FlexCAN channels C, D, E and F are routed to the prototyping area with DB9 connectors to allow additions CAN physical interfaces to be easily integrated. • User prototyping area consisting of a 0,1” grid of through hole pads with easy access to the EVB ground and power supply rails. • Ethernet signals routed to a National Semiconductor physical interface and Pulsejack RJ45 connector with integrated magnetics. • MLB signals routed to SMSC MOST INIC with Tyco Optical Transceiver. INIC JTAG and MLB monitor ports. Support for optional ROM INIC or MLB150 daughter card from SMSC. • 4 active low LED’s and 4 pushbutton switches for development purposes. • Jumper selectable variable resistor connected to ADC channel 0, driving between VRH and VRL. • Liberal scattering of GND test points (surface mount loops) placed throughout the EVB.
圖4.MPC5668G評估板(EVB)功能框圖
圖5.MPC5668G評估板(EVB)電路圖(1)
圖6.MPC5668G評估板(EVB)電路圖(2)
圖7.MPC5668G評估板(EVB)電路圖(3)
圖8.MPC5668G評估板(EVB)電路圖(4)
圖9.MPC5668G評估板(EVB)電路圖(5)
圖10.MPC5668G評估板(EVB)電路圖(6)
圖11.MPC5668G評估板(EVB)電路圖(7)
圖12.MPC5668G評估板(EVB)電路圖(8)
圖13.MPC5668G評估板(EVB)電路圖(9)
圖14.MPC5668G評估板(EVB)電路圖(10)
圖15.MPC5668G評估板(EVB)電路圖(11)
圖16.MPC5668G評估板(EVB)電路圖(12)
圖17.MPC5668G評估板(EVB)電路圖(13)
圖18.MPC5668G評估板(EVB)電路圖(14)
圖19.MPC5668G評估板(EVB)電路圖(15)
圖20.MPC5668G評估板(EVB)電路圖(16)
圖21.MPC5668G評估板(EVB)電路圖(17) 詳情請見: 
MPC5668x[1].pdf
(599.77 KB)
MPC5668GKITUM[1].pdf
(2.05 MB)
MPC5668GKIT_SCH[1].pdf
(396.24 KB)
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