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NO.487-【獵頭職位：深圳需要五位 ASIC RTL Design Engineer】聯(lián)系人：Raymond-Chen,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Job Description: Ø Design RTL for our CPU-centric MachineLearning ASIC chip Ø Optimize timing and power consumption Ø Support functionality debug in simulation andemulation Ø Write timing/power constraint for the design Job Requirement: MUST Ø MS or PhD degree in Electrical Engineering,Computer Science, Physics, Mathematics or equivalent disciplines. Ø MS with > 2 years of industrialexperience; more experiences and capability will correspond to higher joblevels. Ø Excellent RTL design skills with SystemVerilog. Ø Good scripting skills with Python/Perl/Tcl. Ø Solid understanding of low power optimization. Ø Proficient communication in English - bothorally and in writing form. Ø Self-driven, result-oriented; able tomulti-task and determine priorities. Ø A proven fast learner and a team player. PREFERRED Ø Knowledge and experience with RISC-V ISA ishighly desired. Ø Knowledge about CPU architecture and memoryhierarchy. Ø Experience of working with foreign coworkersand remote teams is a plus. 福利：股票期權(quán) 住房補(bǔ)貼 五險(xiǎn)一金 帶薪年假 
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