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As today’s designs increase in complexity, the ability to find and fix design problems through hardware decreases. Designers can’t easily probe internal logic or trace back problems to the source of the problem when looking at a chip. The solution to finding and fixing these problems is through software simulation. Software simulation emulates real time operation of the internal logic as well as the external pins. By probing different locations within the chip, simulation allows designers to trace problems back to the source. The most accurate simulation model is created by the back-end placement tool. However, for larger FPGA devices, the back-end compile times may be significantly longer than the synthesis compiles through Synplify. Synplify is uniquely capable of providing accurate functional simulation models with quick compile times thereby allowing designers to accurately debug functional design problems in a timely manner. This application note describes how to successfully integrate simulation into your design methodology. This integration not only involves the simulation process but additionally uses test benches to run the different types of simulations. Topics to be covered: À Simulation Flow À Simulation Features À HDL Testbenches À Example 1: Functional Simulation (ModelSim) À Example 2: Compiling the Mapped Netlist (Synplify) À Example 3: Mapped-Functional Simulation (ModelSim) À Example 4: Generating Gate Level VHDL/Verilog (Xilinx Alliance) 下載： 
Synplify guide for modelsim.pdf
(110.34 KB)
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