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熱線：021-51875830 62450161 0755-61280252 傳真：021-62450161 業(yè)務(wù)手機(jī):15921673576 詳情請(qǐng)?jiān)L問(wèn)網(wǎng)站：http://www.51qianru.cn 課程目標(biāo) Cadence培訓(xùn)高級(jí)班將首先讓您了解CB板上出現(xiàn)的信號(hào)反射、串?dāng)_、電源/地平面干擾、時(shí)序匹配以及電磁兼容性等一系列問(wèn)題產(chǎn)生的機(jī)理，并掌握其解決方法；然后講解并上機(jī)練習(xí)Cadence的高速 PCB設(shè)計(jì)與仿真工具SPECCTRAQuest的使用。使您在硬件設(shè)計(jì)過(guò)程中，能夠達(dá)到“設(shè)計(jì)即正確”的目的。 培養(yǎng)對(duì)象 在工作實(shí)踐中遇到了高速數(shù)字電路與高速PCB設(shè)計(jì)問(wèn)題；對(duì)高速PCB設(shè)計(jì)感興趣的硬件工程師；已經(jīng)具備一定的硬件開發(fā)經(jīng)驗(yàn)，需要增加就業(yè)競(jìng)爭(zhēng)力的在校碩士及博士研究生；具備非常扎實(shí)的電子工程基本知識(shí)，并積累了相當(dāng)程度的硬件工程師工作經(jīng)驗(yàn)的在校本科生。 班級(jí)規(guī)模及環(huán)境 為了保證培訓(xùn)效果，增加互動(dòng)環(huán)節(jié)，我們堅(jiān)持小班授課，每期報(bào)名人數(shù)限5人，多余人員安排到下一期進(jìn)行。 質(zhì)量保障 1、培訓(xùn)過(guò)程中，如有部分內(nèi)容理解不透或消化不好，可免費(fèi)在以后培訓(xùn)班中重聽； 2、培訓(xùn)結(jié)束后免費(fèi)提供一個(gè)月的技術(shù)支持，充分保證培訓(xùn)后出效果； 3、培訓(xùn)合格學(xué)員可享受免費(fèi)推薦就業(yè)機(jī)會(huì)。 教學(xué)時(shí)間，教學(xué)地點(diǎn) 上課地點(diǎn)：華東師范大學(xué)／銀城大廈（上海市，地鐵3號(hào)線或4號(hào)線金沙江路站旁） 上課地點(diǎn)：地址：深圳市羅湖區(qū)桂園路2號(hào)電影大廈A座2205 （地鐵一號(hào)線大劇院站D出口旁，桂園路和解放路交叉口,近地王大廈） 熱線：0755-61280252 25912501 傳真：0755-25912501 郵編：518001 信箱:[email protected] 客服QQ:812773398 最近開班有周末班/連續(xù)班/晚班 學(xué)時(shí) 課時(shí)： 共9天，每天8學(xué)時(shí)，總計(jì)72學(xué)時(shí) ◆外地學(xué)員：代理安排食宿（需提前預(yù)定） ☆合格學(xué)員免費(fèi)頒發(fā)相關(guān)資格證書，提升您的職業(yè)資質(zhì) 作為最早專注于嵌入式培訓(xùn)的專業(yè)機(jī)構(gòu)，曙海嵌入式學(xué)院提供的證書得到本行業(yè)的廣泛認(rèn) 可，學(xué)員的能力得到大家的認(rèn)同。 ☆合格學(xué)員免費(fèi)推薦工作 課程進(jìn)度安排 課程大綱 第一階段 1 高速PCB設(shè)計(jì)中的理論基礎(chǔ) 傳輸線理論、信號(hào)完整性（反射、串?dāng)_、過(guò)沖、地彈、振鈴等）、電磁兼容性和時(shí)序匹配等等。 2 SPECCTRAQuest設(shè)計(jì)流程 2.1 Pre-Placement 2.2 Board Setup Requirements for Extracting and Applying Topologies 2.3 Database Setup Advisor —Cross-Section —DC Nets —DC Voltages —Device Setup . ??—SI Models —SI Audit 3 拓?fù)浣Y(jié)構(gòu)的抽取與仿真 Extracting and Simulating Topologies 3.1 Pre-Route Extraction Setup—Default Model Selection. 3.2 Pre-Route Extraction Setup—Unrouted Interconnect 3.3 Pre-Route Template Extraction 3.4 SQ Signal Explorer Expert 3.5 Analysis Preferences 3.6 SigWave 3.7 Delay Measurements 第二階段 4 確定和施加約束 Determining and Adding ConstraintsSolution 4.1 Solution SpaceAnalysis: Step 1 to 6 4.2 Parametric Sweeps. 4.3 Constraints : Topology Template Constraints Switch/Settle Constraints Assigning the Prop Delay Constraints Impedance Constraint Relative Propagation Delay Constraint Diff Pair Constraints Max Parallel Constraint Wiring Constraint User-Defined Constraint Signal Integrity Constraints 4.4 Usage of Constraints Defined in Topology Template 5 模板應(yīng)用和基于約束的布局 Template Applications and Constraint-Driven Placement 5.1 Creating a Topology 5.2 Wiring the Topology 5.3 TLines and Trace Models 5.4 Coupled Traces 5.5 RLGC Matrix of Coupled Trace Models 5.6 Crosstalk Simulation in SQ Signal Explorer Expert 5.7 Simulating with Coupled-Trace Models 5.8 Sweep Simulation Results with Coupled-Trace Models 5.9 Extracting a Topology Using the Constraint Manager 5.10 Electrical Constraint Set 5.11 Applying Electrical CSet 5.12 Worksheet Analysis 5.13 Spacing and Physical Rule Sets 5.14 Electrical Rule Set 第三階段 6 基于約束的布線 Constraint-Driven Routing 6.1 Manual Routing 6.2 Routing with the SPECCTRA Smart Route 6.3 Driving Constraints in Routing 7 布線后的DRC檢查和分析 Post-Route DRC and Analysis 7.1 Post-Route Analysis 7.2 SigNoise 7.3 Reflection Simulation 7.4 Reflection Waveform Analysis 7.5 Comprehensive Simulation 7.6 Crosstalk Simulation 7.7 Crosstalk Analysis 7.8 Simultaneous Switching Noise Simulation 7.9 SSN Waveform Analysis 7.10 System-Level Analysis 7.11 A Complete Design Link 7.12 Initialize Design Link 8 差分信號(hào)設(shè)計(jì) Differential Pair Design Exploration 8.1 Types of Differential Pairs in SPECCTRAQuest 8.2 Create Differential Pair Using SPECCTRAQuest 8.3 Create Differential Pair Using Constraint Manager 8.4 Assigning Differential Pair Signal Models 8.5 Preference to Extract Unrouted Differential Pair Topology 8.6 Extracting Unrouted Differential Pair Topology 8.7 Custom Stimulus to Analyze Differential Pair Topology 8.8 Differential Pair Topology Analysis 8.9 Coupled Trace Model and Differential Pair Topology 8.10 Layout Cross-section Editor 8.11 Differential Pair Constraints 8.12 Differential Pair Constraints in the Constraint Manager 8.13 Differential Pair Analysis in the Constraint Manager 8.14 Post Route Extraction |
