關(guān)于ARM CORTEX-A8 S5PV210使用的內(nèi)存相關(guān)配置參考

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S5PV210有兩個(gè)獨(dú)立的DRAM控制器，分別是DMC0和DMC1，其中，DMC0最大支持512MByte，DMC1最大支持1GByte，而 DMC0和DMC1又同時(shí)支持兩個(gè)片選CS0和CS1。S5PV210的內(nèi)存模塊相比2440和6410來(lái)講要更加復(fù)雜一些，要想正確的配置 S5PV210的內(nèi)存，應(yīng)該仔細(xì)閱讀芯片手冊(cè)相關(guān)部分，在配置參數(shù)時(shí)也應(yīng)該適當(dāng)?shù)拈喿x下內(nèi)存芯片的手冊(cè)。

在技術(shù)手冊(cè)里，S5PV210給出了以下幾個(gè)解決方案：

關(guān)于地址映射方面：S5PV210的DMC跟6410和2440的DMC有個(gè)重要區(qū)別，S5PV210可以控制內(nèi)存地址映射，DMC0的地址空間為 0x2000,0000~0x3fff,ffff，DMC1的地址空間為0x4000,0000~0x7fff,ffff，DMC可以通過(guò)配置寄存器來(lái)使 內(nèi)存芯片映射到其內(nèi)存段內(nèi)的適當(dāng)位置。這個(gè)配置在MEMCONFIG寄存器中。

如果設(shè)置chip_base為0x20：

(1)我們掛載的內(nèi)存為128M，那么這個(gè)chip_mask應(yīng)該設(shè)置為0xF8

(2)我們掛載256M內(nèi)存時(shí)，chip_mask應(yīng)該設(shè)置為0xF0

(3)我們掛載512M時(shí)，chip_mask應(yīng)該設(shè)置為0xE0

(4)我們掛載1GB內(nèi)存時(shí)，chip_mask就應(yīng)該設(shè)置為0xC0。

以DMC0為例，當(dāng)DMC0接收到來(lái)自AXI的0x2000,0000~0x3fff,ffff內(nèi)的地址時(shí)，會(huì)作如下處理：

(1)將AXI地址的高8位與chip_mask相與得到結(jié)果，記為X。

(2)將X分別與MEMCONFIG0和MEMCONFIG1的chip_base相比較，如果相等，則打開(kāi)相應(yīng)的片選。

假如掛載的內(nèi)存為128M，且CS0和CS1上分別掛了一片，那么128M=128*1024*1024=0x8000000，則128M內(nèi)存的偏 移范圍應(yīng)該是0x0000,0000~0x07ff,ffff，高位剩余5位，那么，我們把MEMCONFIG0的chip_base設(shè)置為 0x20，chip_mask設(shè)置為0xF8，為了保持內(nèi)存連續(xù)，則需要將MEMCONFIG1的chip_base設(shè)置為0x28，chip_mask 設(shè)置為0xF8，當(dāng)AXI發(fā)來(lái)的地址為0x23xx,xxxx時(shí)，0x23&0xF8得到0x20，所以，會(huì)打開(kāi)片選CS0，當(dāng)AXI發(fā)來(lái)的地址 為0x28xx,xxxx時(shí)，0x28&0xF8得到0x28，所以，會(huì)打開(kāi)片選CS1，依此類推。

特別的，當(dāng)載在的內(nèi)存芯片為8bank（8bank內(nèi)存芯片一般為14/15行地址，10列地址，即容量一般為512M或者1G）時(shí)，由于CS1為 bank2引腳，為了保持CS0時(shí)鐘處于片選狀態(tài)，對(duì)于512M內(nèi)存來(lái)講需要將chip_mask設(shè)置為0xE0，這是因?yàn)?512M=512*1024*1024=0x2000,0000，也就是說(shuō)，512M內(nèi)存的偏移應(yīng)該為0x0000,0000~0x1fff,ffff， 所以高位剩余3位，即0xE0，當(dāng)然了，如果內(nèi)存為1G=1024*1024*1024=0x4000,0000，即偏移為 0x0000,0000~0x3fff,ffff，高位剩余2為，故設(shè)置chip_mask為0xC0。這樣，就會(huì)計(jì)算偏移這兩個(gè)值了。

另外在附上s5pv210（飛凌ok210開(kāi)發(fā)板）的內(nèi)存初始化順序，芯片手冊(cè)上給出了常用內(nèi)存類型的初始化序列，一般如果使用DDR2的內(nèi)存的話，可以按照如下順序進(jìn)行初始化：

Initialization sequence for DDR2 memory type:

1.To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.

2.Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc  bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to 1 to turn on the PHY DLL.

3.DQS Cleaning:Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value  according to clock frequency and memory tAC parameters.

4. Set the PhyControl0.ctrl_start bit-field to 1.  

5. Set the ConControl. At this moment, an auto refresh counter should be off.

6. Set the MemControl. At this moment, all power down modes should be off.

7. Set the MemConfig0  register. If there are two external memo ry chips, set the MemConfig1 register.

8. Set the PrechConfig  and PwrdnConfig registers.

9. Set the TimingAref,  TimingRow,  TimingData and TimingPower registers according to memory AC   parameters.

10.  If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.

11.  Wait for the PhyStatus0.ctrl_locked  bit-fields to change to ‘1’. Check whether PHY DLL is locked.

12.  PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL  should not be off for reliable operation. It can be off  except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force  bit-field to correct value  according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the  PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.

13.  Confirm whether stable clock is  issued minimum 200us after power on.

14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.

15. Wait for minimum 400ns.

16. Issue a PALL command using the DirectCmd register.

17. Issue an  EMRS2 command using the DirectCmd register to program the operating parameters.

18. Issue an  EMRS3 command using the DirectCmd register to program the operating parameters.

19. Issue an  EMRS  command using the DirectCmd register to enable the memory DLLs.

20. Issue a MRS command using the DirectCmd register to reset the memory DLL.

21. Issue a PALL command using the DirectCmd register.

22. Issue two Auto Refresh commands using the  DirectCmd register.

23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.

24. Wait for minimum 200 clock cycles.

25. Issue an  EMRS  command using the DirectCmd register to program the  operating parameters. If OCD calibration is not used, issue an EMRS  command to set OCD Calibration Default. After that, issue an  EMRS  command to exit OCD Calibration Mode  and to program the operating parameters.

26.  If there are two external memory chips, perform steps 14~25 for chip1 memory device.

27. Set the ConControl to turn on an auto refresh counter.

28. If power down modes is required, set the MemControl registers.