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程序是
entity count is
port(
clk,start,stop,reset : in std_logic;
cout ut std_logic_vector(7 downto 0)
);
end count;
architecture behav of count
begin
process(clk,start,stop,reset)
variable c : std_logic_vector(7 downto 0);
begin
if reset='1' then
c:="00000000";
if clk'event and clk='1' then
if start'event and start='1' then
c:=c+1
elsif stop'event and stop='1' then
cout<=c;
end if;
end if;
cout<=c;
end process;
end behav
編譯后出現錯誤:can't infer register for "c[0]" at count.vhd,because it does not hold its value outside the clock edge |
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