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Intersil 公司的ISL70001SEH是集成了MOSFET的輻射和SEE加固的高效同步降壓穩壓器,輸入電壓3V到5.5V,輸出電壓從0.8V到輸入電壓的 ~85%,TJ ≤ +150℃時的輸出負載電流6A,效率大于90%,開關頻率1MHz或500kHz,輻射劑量為100 krad(Si),SEL和SEB LETTH 為86.4MeV/mg/cm2,主要用在FPGA, CPLD, DSP, CPU Core 和I/O電源,低壓大容量分布電源.本文介紹了ISL70001SEH主要特性,方框圖,主/從模式典型應用電路,以及輻射加固FPGA電源參考設計和VIRTEX5MEZPWREV1Z 評估板框圖,電路圖,材料清單和PCB布局圖. Rad Hard and SEE Hard 6A Synchronous Buck Regulator ISL70001SEH The ISL70001SEH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145℃. High integration and class leading radiation tolerance makes the ISL70001SEH an ideal choice to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages. ISL70001SEH主要特性: • ±1% Reference Voltage Over Line, Load, Temperature and Radiation • Current Mode Control for Excellent Dynamic Response • Full Mil-Temp Range Operation (TA = -55℃ to +125℃) • High Efficiency > 90% • Fixed 1MHz Operating Frequency • Operates from 3V to 5.5V Supply • Adjustable Output Voltage - Two External Resistors Set VOUT from 0.8V to ~85% of VIN • Bi-directional SYNC Pin Allows Two Devices to be Synchronized 180° Out-of-Phase • Device Enable with Comparator Type Input • Power-Good Output Voltage Monitor • Adjustable Analog Soft-Start • Input Undervoltage, Output Undervoltage and Output Overcurrent Protection • Starts Into Pre-Biased Load • Electrically Screened to DLA SMD 5962-09225 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Hardness - Total Dose [50-300rad(Si)/s] . . . . . . . . . . .100krad(Si) min - Total Dose [<10mrad(Si)/s] . . . . . . . . . . . . .50krad(Si) min • SEE Hardness - SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min - SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2 max - SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min ISL70001SEH應用: • FPGA, CPLD, DSP, CPU Core or I/O Voltages • Low-Voltage, High-Density Distributed Power Systems 
圖1.ISL70001SEH方框圖
圖2.ISL70001SEH典型應用框圖
圖3.ISL70001SEH 5V輸入電壓和主模式同步應用電路圖
圖4.ISL70001SEH 3.3V輸入電壓和從模式同步應用電路圖 This application note discusses the VIRTEX5MEZPWREV1Zboard, Intersil’s reference design to power FPGA’s in a radiation hardened environment. This particular board is optimized to power a Xilinx’s Virtex-5 FPGA and features the ISL70001SRH and ISL70002SRH, rad hard POL buck regulators along with the ISL75051RH rad hard LDO. The Virtex-5 requires a core voltage of 1.0V, which is supplied by the ISL70002SRH, an auxiliary voltage of 2.5V, which is supplied by the ISL70001SRH, and an I/O voltage of 3.3V which is supplied by the ISL75051RH.
圖5.VIRTEX5MEZPWREV1Z 評估板框圖 The ISL70001SRH and ISL70002SRH are both radiation hardened and SEE hardened high efficiency, monolithic synchronous buck regulators with integrated MOSFETs. These single chip power solutions operate over an input voltage range of 3V to 5.5V and provide a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. The ISL70001SRH can provide up to 6A (TJ ≤ +145°C) of output current while the ISL70002SRH can provide up to 12A (TJ ≤ +150°C) of output current. The ISL75051SRH is a radiation hardened, low voltage, high current, single output LDO specified for up to 3.0A of continuous output current. It can operate over an input voltage range of 2.2V to 6.0V and is capable of providing output voltages of 0.8V to 5V with an external resistor divider. Dropout voltages as low as 65mV can be realized with this device.
圖6.VIRTEX5MEZPWREV1ZA評估板電路圖(1)
圖7.VIRTEX5MEZPWREV1ZA評估板電路圖(2)
圖8.VIRTEX5MEZPWREV1ZA評估板電路圖(3)
圖9.輻射加固FPGA電源解決方案參考設計外形圖 VIRTEX5MEZPWREV1Z評估板材料清單:
圖10.VIRTEX5MEZPWREV1Z 評估板元件布局圖(頂層)
圖11.VIRTEX5MEZPWREV1Z 評估板元件布局圖(底層) 詳情請見: 
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