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ST公司的STR91xFAxxx系列是ARM966E-S™ 16/32位閃存MCU,集成了以太網,USB,CAN,AC馬達控制,4個定時器,ADC,RTC和DMA.處理器核采用哈佛架構,5級流水線,高達96MIPS性能,支持單周期DSP指令,主要用在語音處理,音頻算法和低端圖像.本文介紹了STR91xFA主要特性,方框圖,以及STR912FA實時以太網評估板STEVAL-IFW001V1主要特性,方框圖,電路圖,材料清單和PCB元件布局圖. STR91xFAxxx:ARM966E-S™ 16/32-bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA STR91xFA is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966E-S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich peripheral set to form an ideal embedded controller for a wide variety of applications such as point-of-sale terminals, industrial automation, security and surveillance, vending machines, communication gateways, serial protocol conversion, and medical equipment. The ARM966E-S core can perform single-cycle DSP instructions, good for speech processing, audio algorithms, and low-end imaging. This datasheet provides STR91xFA ordering information, functional overview, mechanical information, and electrical device characteristics. For complete information on STR91xFA memory, registers, and peripherals, please refer to the STR91xFA Reference Manual. For information on programming the STR91xFA Flash memory please refer to the STR9 Flash Programming Reference Manual. For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 Technical Reference Manual. The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die are connected to each other by a custom high-speed 32-bit burst memory interface and a serial JTAG test/programming interface. STR91xFA主要特性: ■ 16/32-bit 96 MHz ARM9E based MCU – ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xFA implementation of core adds high-speed burst Flash memory interface,instruction prefetch queue, branch cache Up to 96 MIPS directly from Flash memory – Single-cycle DSP instructions supported – Binary compatible with ARM7 code ■ Dual burst Flash memories, 32-bits wide – 256 KB/512 KB/1 MB/2 MB main Flash – 32 KB/128 KB secondary Flash – Sequential Burst operation up to 96 MHz – 100 K min erase cycles, 20 yr min retention ■ SRAM, 32-bits wide – 64K or 96K bytes, optional battery backup ■ 9 programmable DMA channels ■ Clock, reset, and supply management – Internal oscillator operating with external 4-25 MHz crystal – Internal PLL up to 96 MHz – Real-time clock provides calendar functions, tamper, and wake-up functions – Reset Supervisor monitors supply voltage, watchdog, wake-up unit, external reset – Brown-out monitor – Run, Idle, and Sleep Mode as low as 50 uA ■ Vectored interrupt controller (VIC) – 32 IRQ vectors, 30 interrupt pins – Branch cache minimizes interrupt latency ■ 8-channel, 10-bit A/D converter (ADC) – 0 to 3.6 V range, 0.7 usec conversion ■ 10 Communication interfaces – 10/100 Ethernet MAC with DMA and MII – USB Full-speed (12 Mbps) slave device – CAN interface (2.0B Active) – 3 16550-style UARTs with IrDA protocol – 2 Fast I2C™, 400 kHz – 2 channels for SPI™, SSI™, or MICROWIRE™ ■ External Memory Interface (EMI) – 8- or 16-bit data, up to 24-bit addressing – Static Async modes for LQFP128 – Additional burst synchronous modes for LFBGA144 ■ Up to 80 I/O pins (muxed with interfaces) ■ 16-bit standard timers (TIM) – 4 timers each with 2 input capture, 2 output compare, PWM and pulse count modes ■ 3-Phase induction motor controller (IMC) ■ JTAG interface with boundary scan ■ Embedded trace module (ARM ETM9) 
圖1.STR91xFA方框圖 STEVAL-IFW001V1, STR912FA實時以太網評估板 Ethernet is a networking standard which has been well known in the computer world as a communication interface mainly for local area networks and Internet access, and proven over the years through its many different versions. While it is indeed a well-tested, fast communication bus, it was originally designed for non real-time (RT) data transfers based on the common medium access and collision detection principle - CSMA/CD. For industrial control it is critical to propagate control data in a fast and deterministic manner through the network to address nodes in limited (short) bus time cycles. Deterministic behavior in terms of RT Ethernet requires a communication process where the time progression can be predicted precisely. This behavior enables synchronization of controlled elements (CNs) in time (process control). It is necessary to eliminate common medium access by using dedicated bus topologies (e.g. daisy chains), by assignment of time slots for each communication device, or by other methods, such as IEEE1588.Industrial Ethernet has been gaining popularity in industrial automation over the last few years. There are numerous standards on the market from different vendors, and many interest groups have been founded around them. The principles of the standards are very similar. The safety requirements of the protocols are extremely important for critical field bus communication. Vendors are defining real-time Ethernet protocols by adding special requirements for bus topologies, bus access, dedicated ASICs and SW stacks on top of the Ethernet standard. Another trend is to keep the smartness of the Ethernet by maintaining its original non real-time usage in asynchronous bus cycle time slots and to handle the critical RT communication in isochronous time slots of the bus cycles. This makes it possible to have one common physical bus (Ethernet) at all levels of communication within a factory, from management level down to the field bus. In this document you will find a description of a system based on the STR912FA ARM966E-S™ microcontroller from STMicroelectronics for Ethernet real-time communication. This user manual describes the STR912FAW44 evaluation board for real-time Ethernet slave communication node evaluation. This board can be daisy chained with others into factory automation field bus systems. The board enables and requires the hooking on of different extensions that fulfill the requirements for different real-time Ethernet protocols on the market (e.g. Powerlink, EtherCAT, and others). For each protocol a special extension, or a programmable one, must be used. The communication between the board and the extension can be done through MII, EMI, SPI™, I2C™ or UART. For Xilinx® Spartan™ FPGA extensions refer to the user manual for the STEVAL-IFW002V1 evaluation board. With additional on-board connectors it is possible to connect industrial I/O cards and motor control boards.
圖2.STR912FAW44實時以太網評估板外形圖 實時以太網評估板主要特性: ● 32-bit STR912FAW44 microcontroller with ARM966E-S™ core running at 96 MHz ● Two fast E-STE101P Ethernet transceivers supporting full duplex communication; available boot configuration settings; up to 32 selectable MII addresses; RJ45 connectors with embedded LEDs ● Two 50-pin header connectors for connecting different on-hook extensions with realtime IP featuring: three MIIs (medium independent interface), EMI (external memory interface), UART, I2C, SPI, external interrupts, 1.8 V, 3.3 V and GND pins ● Connectors for interfacing with industrial I/O cards: CAN, AC MC (motor control),CLT/PCLT (input termination circuit), HSD or SPI HSD (high side driver) ● Power supply using the L5973AD DC-DC converter, and the LF18 for the core supply ● JTAG debug interface connector ● 6 V to 30 V DC power supply voltage range ● One reset and one general-purpose button; two general purpose LEDs
圖3.實時以太網評估板方框圖
圖4.實時以太網評估板電路圖(1):MCU
圖5.實時以太網評估板電路圖(2):連接器,按鈕,LED和CAN
圖6.實時以太網評估板電路圖(3):電源
圖7.實時以太網評估板電路圖(4):以太網1
圖8.實時以太網評估板電路圖(5):以太網2
圖9.實時以太網評估板電路圖(6):控制連接器 實時以太網評估板材料清單:
圖10.實時以太網評估板元件布局圖:頂層
圖11.實時以太網評估板元件布局圖:底層 詳情請見: 
CD00159308[1].pdf
(2.01 MB)
CD00181740[1].pdf
(1.26 MB)
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