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NO.400-【獵頭職位：上海需要一位 Senior IC Design Engineer】聯系人：Sophie-Song,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ 崗位職責： 1、Write Micro-Architecture and Integration Design Spec. 2、Write RTL coding for core and bus standard trace logic, monitor signal map, debug control, etc. 3、Do IP level Linting / CDC check / synthesis / timing analysis / formality check. 4、Assist on Verification Engineer to complete module to top level verification and debugging. 5、Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes. 6、 Take silicon debugging of the related module functionalities. 崗位要求： 1、MSEE with 5+ year experience of sdigital design. 2、Strong skills of Verilog RTL coding, simulation debug and ECO changes with netlist database. 3、Hands on experience in EDA tools such as VCS, Spyglass, DC, PT, Equivalence check, etc. 4、Basic skills of script and be familiar with Shell, Perl, Python, etc. 5、Self-motivated, good team work spirit and communication skills. 6、Following working experiences will be one advantage: (1) Experience in CPU/DSP/GPU design. (2) Experience in AXI/AHB/APB protocols and ARM-based fabric design. (3) Experience in core or bus trace and debug, signal monitoring, PCIe, JTAG related. 
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