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Lattice公司的MachXO2系列是高度可配置的可編程邏輯器件(PLD),具有低功耗,低成本和高系統(tǒng)集成等特性.和MachXO PLD相比, MachXO2系列邏輯密度增加3X,嵌入存儲器增加10X,靜態(tài)功耗降低100X,而成本降低30%,因此廣泛用在系統(tǒng)應(yīng)用如通信架構(gòu),計(jì)算,高端工業(yè)和高端醫(yī)療以及消費(fèi)類電子如智能手機(jī),數(shù)碼相機(jī),GPS設(shè)備,移動(dòng)計(jì)算等,本文介紹了MachXO2控制開發(fā)板主要特性,方框圖,電路圖和材料清單. The MachXO2 family of infinitely reconfigurable Programmable Logic Devices (PLDs) offers designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. In addition, the MachXO2 family includes hardened implementations of some of the most popular functions used in system applications (telecom infrastructure, computing, high end industrial, high end medical) and consumer applications (smart phones, GPS devices, mobile computing, digital cameras). These include User Flash Memory (UFM), I2C, SPI and timer/counter. Thus, through the provision of these features and capabilities, the MachXO2 family offers designers a "Do-it-All PLD" for low density applications. The MachXO2 Control Development Kit provides a full featured development platform to prototype system control designs using MachXO2 PLDs. The kit features the MachXO2-1200HC device, a Power Manager II ispPAC-POWR1014A, 128Mbit LPDDR memory, 4Mbit SPI Flash and a microSD card socket. Using the preloaded Control system-on-chip (SoC) design you can test within minutes board control functions such as power supply sequencing, reset distribution, power supply monitoring and data logging using the Power Manager II POWR1014A and 8-bit LatticeMico8™ microcontroller. Other downloadable demonstration examples for the MachXO2 Control Development Kit includes a Display Interface design. You can then build your own designs using the free downloadable reference design source code, implementing these features in less than an hour. The board features USB channels for JTAG programming and debugging from a host PC. A 16x2 header provides access to a variety of I/O banks of the MachXO2 device and the on-board SPI and I2C buses. The board can be controlled with a menu driven interface via terminal programs running on a host PC. MachXO2控制開發(fā)板主要特性: MachXO2 PLD: LCMXO2-1200HC-MG132CR1 Power Manager II ispPAC-POWR1014A 128Mbit LPDDR Memory 4Mbit SPI Flash Current and Voltage Sensor Circuits microSD Memory Card Socket Audio Output Channel Expansion Header for JTAG, SPI, I2C and PLD I/Os LEDs & Switches RS-232/USB Interface JTAG Interface SPI Interface I2C Interface Programmed via Standard USB Cable QuickSTART Guide Marked for CE, China RoHS Environment-Friendly Use Period (EFUP) and Waste Electrical and Electronic Equipment (WEEE) Directives 
圖1.MachXO2控制開發(fā)板方框圖
圖2.MachXO2控制開發(fā)板外形圖
圖3.MachXO2控制開發(fā)板電路圖(1)
圖4.MachXO2控制開發(fā)板電路圖(2)
圖5.MachXO2控制開發(fā)板電路圖(3)
圖6.MachXO2控制開發(fā)板電路圖(4)
圖7.MachXO2控制開發(fā)板電路圖(5)
圖8.MachXO2控制開發(fā)板電路圖(6)
圖9.MachXO2控制開發(fā)板電路圖(7)
圖10.MachXO2控制開發(fā)板電路圖(8)
圖11.MachXO2控制開發(fā)板電路圖(9)
圖12.MachXO2控制開發(fā)板電路圖(10)
圖13.MachXO2控制開發(fā)板電路圖(11)
圖14.MachXO2控制開發(fā)板電路圖(12) MachXO2控制開發(fā)板材料清單(BOM):
詳情請見: http://www.latticesemi.com/documents/doc41112x63.pdf |
