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NO.352-【獵頭職位：上海需要兩位 verificationengineer 】聯系人：Lincy-Cao,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Job description: 1. Work with designer to get a fulldeep insight on the design and develop stressful test plan for SoC and IPs； 2. Build test bench and createtestcase to ensure maximum coverage； 3. Run simulation in both RTL andnetlist level, debug and fix issues, create test reports； 4. Develop verification IP whichcan be reused at different level verification； 5. Co-work with FPGA engineer toprepare test vector, support test and debug； 6. SoC system performanceprofiling, system stress test； 7. Explore advanced verificationmethodology, optimize the verification process/environment to improveefficiency and quality； 8. Support DV manager to do theverification quality control and sign-off the DV task. Requirement: 1. MSEE/MSCS degree or equivalent； 2. Minimum 8 years’ experience indesign verification field； 3. Good knowledge inSystemVerilog, C/C++ and UVM； 4. Good knowledge in the SoCarchitecture, AXI/AHB protocol. Experienced in full chip verification plan,execution and sign-off； 5. Experienced in system performancetest； 6. Strong communications skillsand capability； 7. Self-motivated and good teamplayer. Niceto have： 1. Strong Programming in Perl,Python； 2. Good digital signal processingbackground and be familiar with video processing algorithm, be familiar withMATLAB； 3. Experienced in low powerverification； 4. Be familiar with FPGA debug. 福利：五險一金 年假+獎金 |
