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【獵頭職位：上海需要一位PDK and RFA/SoC CAD Engineer】聯系人：Grace-Tai,郵箱：hr@kthr.com，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Overview: 1、Connectivity is looking for a self-drivenindividual who enjoys working with engineers in various areas of designdisciplines to solve design flow issues including analog front-end simulation,custom design environment, automation and synthesis, EM analysis andInductor/Transformer synthesis, physical design verification, parasiticextraction, DFM, and tapeout. You willbe working with a highly motivated and “can do” PDK and CAD development engineering team； 2、Design, develop and maintain PDK, CAD, PhysicalVerification, Parasitic Extraction, and design methodology； 3、Work with team members in United States and/orAsia to provide CAD support to RF/A and SoC Physical Design (PD) designers. ResponsibilitiesInclude: 1、Maintain and enhance methodologies for chipassembly, device and parasitic extraction, transistor level simulation, andphysical verification such as LVS, DRC, PERC, and ERC； 2、Customize foundry model files and PDK toaccommodate design needs； 3、Develop PCELLS PDK and enhance RF/A design flowfor analog design； 4、Set up transistor level simulation andmixed-signal simulation； 5、Set up CAD environment for EDA tools andrevision control system for design databases； 6、Enhance and customize foundry rules decks forphysical verification (including SoC PD) and DFM requirements； 7、Set up extraction flow for post layoutsimulation； 8、Interface with and provide CAD support toengineers at multiple geographic sites； 9、Support all tools and methodologies for bothback end (analog/digital layout tools, physical verification, parasitic extraction,and DFM) and front end (transistor simulation and mixed mode simulation)； 10、Provide training sessions on tools usage todesigners. Qualifications: Education: MS inElectrical Engineering, with CSEE as a plus, or equivalent. Experience: 1、Recent graduate or, 3 or more years of analogCAD support and/or analog circuit design experience with strong programmingand/or scripting ability； 2、Knowledge of static timing analysis andplace-n-route flow is a plus； 3、Strong programming and scripting ability is amust. Desired Skills: 1、Ability to read schematics, layout, Spectre,CDL, Verilog, LEF, DEF, and SPEF； 2、Excellent team work, communication, andinterpersonal skills； 3、Strong understanding of analog EDA design andsimulation tools； 4、Strong understanding of Calibre physicalverification and parasitic extraction tools and flows； 5、Knowledge or hands-on experience in statictiming analysis flow； 6、Knowledge or hands-on experience in RF/A designand simulation； 7、Knowledge of CMOS and FINFET device leveltransistors and process； 8、Knowledge of and experience in mixed signalsimulation and setup is a plus； 9、Understanding or ability to write Verilog modelsof analog blocks is a plus； 10、Understanding or ability to create mixed signaltest benches； 11、Fluent in scripting languages in PERL, SHELL,PYTHON, Cadence SKILL, and TCL； 12、Knowledge of NIS, compute server and fileserver. |
