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【獵頭職位：上海需要一位驗證工程師/經(jīng)理】聯(lián)系人：Jessy-He，郵箱：hr@kthr.com，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Key responsibilities/duties: 1、Verification of Block level or SoClevel design using random methodologies Test Planning, Implementation andExecution； 2、Develop System Verilog (UVM) randomsequences and methods； 3、Maintain and Interface withexisting random generators, models Integration of random modules to varioustestbenches； 4、Executing verification throughdirected and random tests for its functionality and interface protocols andtracking bug reports； 5、Creation of the needed testlibraries, simulation models. Debugging regression failures and identify thecause. Key skills & knowledge: 1、Strong documentation andcommunication skills； 2、Complex IP/ SOC Design Verification,direct experience in IP/SOC ； 3、Good knowledge of SystemVerilogand UVM； 4、Good knowledge ofVerilog/C/C++/System C is a plus. |
