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【獵頭職位：上海需要一位 Staff Verification Engineer】聯系人：Lincy-Cao，郵箱：hr@kthr.com，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Responsibilities: -Understanding the expected functionality of designs. -Developing testing and regression plans. -Designing and developing verification environment. -Running RTL and gate-level simulations/regression. -Code/functional coverage development, analysis and closure. Qualifications Experience & Skill: 5 Years -Minimum of five years experience. -Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills. -Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. -Candidate should be familiar with industry standard ASIC design and verification tools and flow. -Good knowledge DDR protocol and computer system achitecture would be an added advantage. -Good knowledge of Perl and shell programming would be an added advantage. -Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). -Knowledge in ASIC/FPGA design process and verification tools. -Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). - Scripting and automation skills (tcl, perl, makefile etc) a plus. -Familiar with C/C++. -Knowledge of DDR protocol a plus. -Independent and self-managing. 
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