作者:myshitshit 這次來講講電路設計公司里邊各個角色的分工以及可能的職業命運 先講講國內集成電路設計公司里需求最普遍的數字電路工程師了 為了明了,先拿一個招聘啟事來說事。 Senior ASIC Design Engineer Responsibilities: Work with a team of hardware and software engineers to define the high-level architecture Share in definition of micro architecture of next generation ASIC Own RTL design for portions of the chip, contribute to Design Verification and Synthesis Active role in Static Timing analysis, floor-planning, IP selection and all aspects of ASIC implementation System level validation in FPGA environment, device and system bring up and qualification Qualifications: 10+ years of experience in high-performance design / micro-architecture 10+ years of experience in Verilog RTL development experience in a CPU/SOC and ASIC environment Must have a strong background in all aspects of ASIC implementation, especially with Synthesis flow, Static Timing Analysis, Floor-planning and I/O ring design Understanding of L2 Ethernet switching protocols (VLAN, Broadcast/Multicast), PCI Express and Storage protocols are desired Experience with FPGA implementation flows is a plus Strong problem solving and debugging skills Experience with silicon and system bring up Excellent communication skills Candidate will likely have an MS EE with 10+ years of experience 可以看到這個是招聘高級工程師的廣告,這里比較清楚的定義了一般數字電路工程師要做的事情,包括系統層次的軟硬件劃分,模塊定義,IP核選用,HDL代碼編寫,驗證,綜合,時序分析,系統原型驗證等龐雜的事物,當然這是對帶頭大哥的要求,剛進門的小弟,一般都是從其中的一樣開始做起。招收的初級工程師,一般只要求會些HDL代碼,會幾種總線協議,懂一點算法知識,能把確定了算法功能的模塊用HDL代碼寫出來,做簡單的仿真。 日常工作中,邏輯設計工程師需要打交道最多的,就是HDL文本編輯器跟邏輯仿真器,當然還要寫相關的文檔,需要配合工作最多的人,除了領頭的大哥,就是負責算法設計的人和負責驗證的人。單純的模塊邏輯設計,可以說是集成電路設計環節中門檻最低的一個,基本上有門級數字電路知識,會寫Verilog,能看懂英語,就可以勞動了。所以這個隊伍里,會有一些連pn節是啥都不清楚的人做,而且完全能夠勝任。 這個工作干一段時間,基本感覺就是一部翻譯機,把matlab或者C代碼翻成Hdl,然后掛在總線上,想工作上有些突破,無非就是再接觸一些系統層面的或者物理實現以及dft的東西,向前面所說高級工程師發展,或者有人憑著熟練的編碼去轉行做FPGA開發,然后變身應用工程師以及銷售,當然也有極少人變成倒賣EDA工具的販子。基本來說這個工作需要2-3年就可以完全熟練,之后就是高產操作員了。一般公司開的職位工資從畢業生到高級工,在6-20k之間。當然領導級的不在此列。 對于還在夢想進入這個職業的人,可以熟悉一下技能跟工具。 Verilog VHDL編碼 linux基本操作,emacs,gvim編輯器使用 questasim,incisive,vcs仿真器使用 perl,tcl腳本語言 各種總線協議,音視頻通信算法大體了解,ARM/MIPS處理器基本知識 再來看看邏輯綜合工程師的工作,以下是工作描述以及入職要求。 Job Requirements and Qualification You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and Cadence design tools and flows. Minimum Requirements: SOC level Synthesis / STA. Experienced with Verilog/VHDL digital design Hands on experience with constraints development Hands on experience with Synopsys design compiler and ICC SoC implementation experience such as full chip level synthesis Pre-P&R timing closure Hands on experience with Spyglass rule checking, netlist equivalence checking, and gate-level simulations Experience with various synthesis options to optimize the power of the Design. Work with Place and Route peers for timing closure Good Knowledge of Static Timing Analysis and Place and Route. Familiarity with various interface technologies including MIPI, USB, I2C, GPIO, DDR etc Familiarity with ASIC design flows for deep sub micron technologies Familiarity with FPGA design flow is plus Preferred Requirements: Familiarity with image processing is a strong plus Responsibilities In this role, the candidate will work with designers and understand the complexity of the blocks and interfaces. A candidate will work with the ASIC design team and will participate in the development of netlist generation from synthesis. A candidate will also support the design team to do simulations . Responsibilities include: reading the RTL code. Generating chip level timing constraints. Validating the RTL inputs. Analyzing the power for the design and optimizing for speed/area/power. Understand and drive the pre-synthesis chip-level timing to ensure that synthesis and layout level timing and other specifications can be achieved. Support chip level verification and physical design timing closure. 這個工作只有一個目的,就是把HDL代碼變成網表,這個對于做FPGA來說大多時候就是按一下就自動生成了,對芯片這事做起來并不像說的這么輕松,首先要清晰了解整個芯片的時鐘復位電源系統,寫出約束文件,把HDL代碼用工具轉換為netlist,并且分析時序報告,比較網表與代碼的邏輯一致性,有些dft插入工作也要在這里完成。這個工作除了要求熟悉電路本身的結構外,主要要求對綜合工具有深入了解,并對選用的工藝熟悉。不同的綜合策略,得出的網表結果跟所費時間是有差異的,許多年來DC一直是首選工具,每出一個新版本,綜合工程師都要看看有什么新搞法。這個職位雖然需要寫的代碼沒有邏輯設計驗證那么多,但是一般的設計都要來回綜合很多次,大芯片每次所費時間又長,等待的也是很讓人痛苦。這個工作需要打交道最多的人是邏輯設計人員跟物理設計人員。 這個職位相對來說屬于整個數字流程中要求比較高的崗位,除了對工具的熟悉,一般也要求熟練使用腳本語言。這個崗位基本不會招收剛畢業的學生,大部分是公司內部做邏輯設計的人自學一下然后轉崗專門搞這個,一般國內公司里邊專業做綜合的人數量很少,所以這些人跳槽的話公司都會加錢留住,當然這些人的責任也是重大的,如果芯片掛了,這些人是沒法再老板那里交差的。這個崗位基本招聘的都是有些資歷的工程師,一般工資都在15k以上。 當然這個職位想轉行就比較難點,一般都是混時間久了變成公司的臺柱子之一,或者去賣DC,不過貌似國內做DC使用培訓銷售的就那么幾個人吧,不同城市的設計服務中心講課的都是那個面孔。 |