What’s New in CR-5000 V14

發布時間：2012-8-13 08:36 發布者：SoarphysYan

The latest release of our advanced design suite for PCB and advanced packaging design. + CR-5000 revision 14 offers a wide array of enhancements to help you streamline your design process. We have achieved sizeable performance gains in placement and routing, which account for 60-70% of PCB design work. New features in CR-5000 include improvements in performance and usability to make design work more efficient. In addition to the features highlighted below, more information is available in the product release notes.
Increased automationSet-up time for high-speed constraints is reduced with automatic, rules-driven differential pair creation in Board Designer. Conducting EMC-specific design rule checks is made easy with new options that allow automatic rule assignment by pre-defining net names in the EMC Adviser rules utility. Engineers can reduce time and effort conducting simulation and analysis in Lightning with options for batch simulation on a large selection of nets with varying parameters to verify PCB performance under specified constraints. For multi-gigahertz circuit simulations, users can specify the default simulator – either the SI engine of Lightning or HSPICE – simplifying the process for simulation and analysis.
PerformanceImprovements include faster processing when generating and correcting solid and meshed copper areas, especially where cut-out shapes and other conductive figures exist. Lightning’s SI Simulator kernel has improved performance for DC pre-analysis cases, including S-Parameter models or large circuits.
Routing * Routing technology from the Lightning high-speed design environment has been incorporated directly into the core functionality of Board Designer. Trunk routing allows you to handle multiple signals at the same time by grouping them together and routing them as a bundle. Automatic trace lengthening creates serpentine wiring for controlling the timing of high-speed signals.
Improved ease of useDefining rules and constraints for nets, extended nets, and differential pairs has been simplified with access to the net attributes dialog when selecting a signal directly within the canvas. This avoids the need to access the net objects dialog for setting attributes. Designers can also save time with options to delete self-healing copper areas and the reference template area at the same time.
Enhanced reporting and review +New batch reports are available to enrich design reviews with complete wire length information that can be exported to a spreadsheet. Results include total wire length of nets and extended nets, total via count, and other physical constraints specified in the design. Collaboration during design reviews are enhanced with new mark-up features in Board Designer, allowing users to input comments or flag items to be reviewed within the design, with bi-directional exchange of mark-ups with Board Viewer Advance.
IC and PCB co-design Co-designing high pin count devices, such as FPGAs or ASICs, is improved with tighter collaboration between Graphical Pin Manager (GPM) and System Designer or Design Gateway. Engineers can update the logical circuit and PCB design with revised, divided component symbols and key part information. Both System Designer and Design Gateway support output for Intel Schematic Review to improve collaboration when using Intel devices and interacting with Intel’s review services.
Database revision control * CR-5000 design data can be freely converted between versions 10 through 14.
* Windows version only.

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