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NO.612-【獵頭職位：上海、成都需要多位 SoC Architect】聯(lián)系人：Edward-Duan,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 崗位職責(zé)： 1、Be responsible for the architecture design of CPUsubsystem in SoC, including the design of cache. structure、memory hierarchy and bus architecture. 2、Be responsible for CPU and bus fabric performance evaluation and optimization. 3、Be responsible for SOC security mechanism design which is based on ARM Trust Zonestructure. 4、Be responsible for CPU low power design to implement DVFS. 5、Support the software team to design the framework of the software. 6、Support function safety manager to design the function safety mechanism for CPU subsystem. 7、Co-work with the verification team to formulate the verification plan and continue to cooperate to ensure that the verification coverage reaches the convergence goal. 8、Co-work with the Physical implementation team and deeply participate in the back-end task to ensure the good PPA result and smoothy timing closure. 9、Co-Work closely with the prototype design team to support chip verification and software development. 10、Co-Work with the Post-silicon validation team to do chip bring-uptest and performance bench mark test. 崗位要求： 1、Be familiar and hands on experience to design high performance scaling platform for heterogeneous multiprocessor HPC. 2、Be familiar and hands on experience to design a cache system for HPC. 3、Be familiar to co-optimization with the Linux SMP software team 4、Be familiar with ARM processor architecture, experienced in ARM high performance Cortex A series core integration and implementation. 5、Be familiar with ARM Trust Zone security schema, Be familiar with MMU and Cache behavior. 6、Be familiar with CHI, ACE, AXI5/4, AHB, APB bus protocols and CMN/CCI/NOC fabric structure. 7、Be familiar with DDR behavior, has rich experience in DDR bandwidth optimization 8、Being familiar with Fusarequirement andmechanismis a big plus 9、Being familiar with Linux kernel is a big plus. 10、Being familiar with DFT structure is a plus. 11、Master’s degree or above in CS, EEor other related majors. More than 15 years chip design experience in CPU or cache system and 5-year SoC architecture experience at least 福利：五險一金 不打卡彈性 純外資風(fēng)格 牛人多 國外團隊歸國 chiplet艙駕一體芯片 
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