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NO.615-【獵頭職位：北京需要多位 資深邏輯驗(yàn)證工程師/驗(yàn)證經(jīng)理】聯(lián)系人：Edward-Duan,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機(jī)微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 崗位職責(zé)： 1、Understand the expected functionality of designs; 2、Design and develop verification environment; 3、Run RTL and gate-level simulations/regression; 4、Code/functional coverage development, analysis and closure; 5、Release the documents during the verification flow, such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc. 崗位要求： 1、Minimum of 4 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.); 2、Familiar with design and verification languages (Verilog, System Verilog, UVM etc.); 3、Script and automation skills (tcl, perl, makefile etc) a plus; 4、Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design; 5、Independent and self-management; 6、Cooperative and proactive in daily work. 福利：五險一金 彈性工作 股票期權(quán) 氛圍好 大牛
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