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下面是代碼
module IO_Expander (CS, RD, WR, RST, CONF, LOAD, MODE,
MCU_IO, IO_PortA, IO_PortB, IO_PortC, IO_PortD);
input CS, RD, WR, RST, CONF, LOAD, MODE;
inout [7:0] MCU_IO, IO_PortA, IO_PortB, IO_PortC, IO_PortD;
wire writeA, writeB, writeC, writeD, read, en_IObuf, reset;
wire [1:0] Latched_Addr;
wire [3:0] inv_address;
wire [7:0] rbuf, wbuf_A, wbuf_B, wbuf_C, wbuf_D, inbuf, outbuf, Latched_en;
latch_io write_instA(.enable(writeA),.reset(reset),.data(MCU_IO),.q(wbuf_A));
latch_io write_instB(.enable(writeB),.reset(reset),.data(MCU_IO),.q(wbuf_B));
latch_io write_instC(.enable(writeC),.reset(reset),.data(MCU_IO),.q(wbuf_C));
latch_io write_instD(.enable(writeD),.reset(reset),.data(MCU_IO),.q(wbuf_D));
latch_io read_inst(.enable(read),.reset(reset),.data(inbuf),.q(rbuf));
reg_Addr register1_load(.enable((CONF & LOAD) | CS),.reset(reset),.data(MCU_IO[1:0]),.q(Latched_Addr));
reg_en register2_load(.enable(CONF | CS),.reset(reset),.data({inv_address[3:0],MCU_IO[5:2]}),.q(Latched_en));
tri_buffer wPortA(.in(wbuf_A),.oe(Latched_en[0]),.out(IO_PortA));
tri_buffer wPortB(.in(wbuf_B),.oe(Latched_en[1]),.out(IO_PortB));
tri_buffer wPortC(.in(wbuf_C),.oe(Latched_en[2]),.out(IO_PortC));
tri_buffer wPortD(.in(wbuf_D),.oe(Latched_en[3]),.out(IO_PortD));
tri_buffer rPort(.in(rbuf),.oe((en_IObuf & ~MODE) | (en_IObuf & CS)),.out(outbuf));
mux4_8bit mux0(.inA(IO_PortA),.inB(IO_PortB),.inC(IO_PortC),.inD(IO_PortD),.sel(Latched_Addr),.mux_out(inbuf));
mux4_1bit mux1(.inA(Latched_en[4]),.inB(Latched_en[5]),.inC(Latched_en[6]),.inD(Latched_en[7]),.sel(Latched_Addr),.mux_out(en_IObuf));
assign inv_address[3:0] = {~MCU_IO[5], ~MCU_IO[4], ~MCU_IO[3], ~MCU_IO[2]};
assign MCU_IO = outbuf;
assign reset = RST | CS;
assign read = RD | CS;
assign writeA = (Latched_Addr[0] | Latched_Addr[1] | WR) | CS;
assign writeB = (~Latched_Addr[0] | Latched_Addr[1] | WR) | CS;
assign writeC = (Latched_Addr[0] | ~Latched_Addr[1] | WR) | CS;
assign writeD = (~Latched_Addr[0] | ~Latched_Addr[1] | WR) | CS;
endmodule |
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