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NO.474-【獵頭職位：上海需要兩位 Senior/Principal Analog Layout Engineer】聯系人：Edward-Duan,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Job Description: 1.Participate in or lead the layout design supportby performing custom floor planning, custom routing, and physical verificationof analog and mixed-signal block or macro levels, IOs or IO ring, etc. IP levellayout designs. 2.Participate in or lead the layout verificationwith LVS/DRC/Antenna support, quality check and documentation. 3.Be responsible for design rule and schematicverification, manufacturability, verification, bonding, stepper utilization,electro migration and ESD verification, to ensure that all layout designoperations meet design, mask, and fab requirements. Be responsible foridentifying and correcting the failure prone circuits and layout structures viacollaboration with circuit designers. 4.Participate in or lead the maintenance andevolvement of the layout design & CAD methodologies and flows. 5.Participate in or lead the task/project planning,scheduling, and executing to meet schedule and milestones. 6.Work closely with *** global design teams inIndia, US, UK, China, etc. to achieve the best efficiency and effectiveness. 7.Assist the Design Director in managing anddeveloping the team competencies; and in recruiting, training and coaching. 8.Supervise a group of Analog Layout Engineers andSenior Analog Layout Engineers when assigned. JobRequirement: 1.Must have deep knowledge and experience in customanalog and mixed signal IC transistor level layout design of block or macrolevels, IOs or IO ring, and full chip level layout designs. 2.Must have solid experience with CadenceVirtuoso-XL and Virtuoso-L, Mentor Graphic Calibre, Cadence Assura/PVS, andLinux Operating System. Must be familiar with P&R methodologies andflows. 3.Must have High level proficiency ininterpretation and customization of calibre/assura DRC, LVS, ERC, antenna ruledecks and post layout extraction. 4.Must have good understanding of analog layouttechniques, such as device matching, shielding, LOD/STI, WPE, PSE, OSE, RFconcepts, minimizing parasitics and high power routing etc. 5.Must have good understanding of CMOS fabricationconcepts and process. 6.Must have knowledge of latch-up prevention andESD protection scheme. 7.Preferred knowledge of skill, perl, c-shell, andtcl programming, to be able to automate repeatable tasks for productivityimprovements in layout. 8.Preferred experience in flow/methodology/CADset-up. 9.Must have good verbal and written communicationskills and experiences in creating documents using Microsoft Office andMicrosoft Power Point. 10.Must have the ability to communicate effectivelywith internal and external interfaces. 11.Must be a self-starter with the ability toproactively propose technically competent solutions; must be result-orientedand have the skills to manage time efficiently. 12.Preferred experience in analog and mixed signalIP layout such as LDO, brown-out, oscillator, PLL, DLL, op-amp, programmablegain amplifier (PGA), programmable threshold detector, zero-crossing detector,resistive temperature detector (RTD), bandgap voltage reference, ADC, DAC,analog comparator, temperature sensor, etc. 13.Language skills:English, fluent conversation,reading and writing；Chinese mandarin, native speaker 14.Relevant experience:Minimum 6-year experience inanalog and mixed signal circuit design 福利：五險一金 帶薪年假 員工福利 |
