|
NO.465-【獵頭職位：北京/上海需要一位 Senior physical designengineer leader】聯(lián)系人：Edward-duan,郵箱：hr@kthr.com，微信也可查詢職位了！打開(kāi)手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 崗位職責(zé)： Ø Execute the whole Physical Design flow includeFloorplan/Placement/CTS/Routing/Physical Verification Ø Work with front end design Engineers to achieve timing closure for bothpartition level and full chip level Ø IO ring design Ø Cross talk Analysis Ø IR Drop and Power Integrity Analysis Ø Execute ECO's. Ø Develop and enhance entire physical design flow at both chip and blocklevel. 崗位要求： Ø BS/MS in Electrical or Computer Engineering with 8+ yrs experience inphysical design Ø Experience with advanced process(at least TSMC 28nm process), experiencewith hierachical design flow. Ø Hands-on experience in top module physical design. Ø Hands on experience in logic synthesis and equivalence checking/FVrequired. Ø Expertise in physical design and optimization e.g. placement, routing,cell sizing, buffering, logic restructuring, etc. to improve timing and powerrequired. Background in implementing them through ECOs required. Ø Understanding of DFT logic and hands-on experience in design closuretaking into account DFT logic required. DFT timing closure for various modese.g. scan shift and capture, transition faults, BIST, etc. would be a plus. Ø Expertise in analyzing and converging crosstalk delay, noise glitch, andelectrical/manufacturing rules in deep-sub micron processes Ø Understand process variation effect modeling and experience in designconvergence taking into account variations required. Ø Experience in critical path planning and crafting. Experience in circuits,SPICE simulations, and/or transistor level STA would be a plus. Ø Expertise and in-depth knowledge of industry standard EDA tools required. Ø Proficiency in scripting languages, such as, Perl, Tcl, Make, etc.Experience in methodology and/or flow automation would be a plus. 福利：上班彈性 獎(jiǎng)金+股票
|
