|
電源(power supply)
原理圖(schematic) MY-I.MX6系列核心板，只需要一個5V電源（持續供電電流不低于2A，峰值2.5A-3A）輸入即可。詳見下圖。
MY-I.MX6 series of core board only needs 5V power source（constant current is not small than 2A，peak value 2.5A-3A）as an input。details as below。
![]()
如果是直接的5V輸入，5V的電源一定要做過壓保護，過壓保護電路參考如下。
if it is a direct 5V input，5V power source need a over voltage protection，the protection circuit can be designed with following reference。
![]()
如果是高電壓輸入通過DCDC轉換成5V，核心板會輸出一個3P3V的電源，此電源的電流不超過500mA。如果底板上面3.3V的電流非常小，可以直接采用此3P3V作為底板的供電電源，如果用3P3V作為底板供電電源，請在3P3V電源上串上500mA的保險絲。
if it is high voltage input to be converted to 5V through DCDC principle,the core board will output 3P3V power source with a maximum current 500mA of which can be used as power supply for base board if current with 3.3V on the base board is too small，in this case,please put in serial a fuse for this 3P3V power source 。
由于底板上面的3.3V電壓通常會超過500mA，一般用戶會單獨通過DCDC或者LDO產生3.3V。
since current with 3.3V on the base board is usually over 500mA，normally users will generate a another 3.3V through DCDC or LDO。
注意：底板的3.3V的電源，一定要通過核心板的3P3V來做使能控制，而不能夠直接由底板上面的其他電源產生。如果底板上面還有其他電源，也必須有3P3V來做使能控制。此點是由于I.MX6芯片決定的。
note：enable control must be done for 3.3V on base board by 3P3V on core board instead of being conducted by other power sources on the base board.if there are other power sources on base board,their enable controls must be conducted by 3P3V as well,this is up to the nature of I.MX6 chip。
參考電路如下：
reference circuit as below：
![]()
PCB 核心板5V電源輸入處要放置大的儲能電容，確保CPU在瞬間增加負載的時候不至于斷電。如果有過孔，確保過孔的電流至少能夠通過3A的峰值電流，可以多打一些過孔增加電流。
capacitor with big capacity should be placed near 5V input on core board, to ensure contituous power supply even when sudden extra load is added for CPU。if there is via hole,need to make sure via hole can go through 3A peak current,more via holes can be built to increase current。
串口設計(serial port design)
原理(principle) 串口設計上面，經常會碰到的問題是RXD跟TXD的方向接反。參考原理圖中的網標表示如下
for serial port design,common questions arising are inversion between RXD and TXD。network standard in the schematic as below
![]()
TXD——CPU輸出
TXD——CPU output
RXD——CPU輸入
RXD——CPU input
PCB 注意：在設計底板的時候，我司提供了底板的原理圖和PCB圖，串口我司采用的是母頭的接口。務必確保用戶在設計的時候也使用的是母頭，如果要更換成公頭。RS232信號要更換。公頭母頭的詳細信息請上網查詢
note：we can provide schematic and PCB diagram for design of base board,our serial port is female head as connector.please assure your design to be consistent with our offer,if change serial port to be male head connector,then RS232 siganl connector head need to be changed accordingly.For the details of male and female head connector,please get on internet for consuls.
SD卡設計(SD card design)
原理(principle) 用戶在設計SD卡的時候，針對IO的上下拉，請嚴格參考原理圖，過多的上下拉可能會導致SD卡不能夠正常的工作。參考圖見下面
for users'design of SD card,please follow strictly schematic to arrange IO dropdown，excessive dropdown will enable SD card not to work normally。reference diagram as below
![]()
注意：如果用戶不需要SD卡，要換成TF卡，由于TF卡是沒有寫保護這個功能的。寫保護信號（SD3_RST/SD3_WP）要下拉，而不能夠直接懸空。如果TF卡選用的是熱插拔卡座，一定要清楚TF卡的檢測管腳是哪個。一般情況是插卡之后，檢測管腳接地，此時插入檢測管腳（KEY_COL/SD3_CD_B）要上拉。如果TF卡選擇的是翻蓋式非可插拔卡座。寫保護信號上拉，同時插入檢測信號要接地（相當于始終插入了卡）
note：if users don't need SD card,but need TF card,since TF card doesn't have function of write-protect.Write-protect signal（SD3_RST/SD3_WP）need to pull down,which can't be hanged direclty in the air.If TF card booth is designed with hot swap，must make clear which pin of TF card is for dectetion。normally when insert the card,detection pin will be grounded，the inserted detection pin KEY_COL/SD3_CD_B）need to pull up.If TF card booth is designed with flip type,write-protect need to pull up,at the same time the inserted detection signal need to be grounded（just as a card is kept in the booth）
如果要增加ESD保護。確保接在SD_CLK信號上的ESD的電容值很小。
if need additional ESD protect,please ensure a small capacity value on SD_CLK signal。
PCBSD0，SD1，SD2，SD3，CMD，CLK信號要做等長處理。ESD原件要跟SD卡座非常接近。
SD0，SD1，SD2，SD3，CMD，CLK signal need an equal treatment。ESD originals need to be very close to SD card booth。
SATA設計(SATA design)
原理(principle) SATA的原理相對簡單，確保方向正確。由于一般SATA盤的電流比較大，5V輸入電流要不低于3A為好。
SATA principle is simple by contrast, only need to ensure a correct direction. since current on SATA is normally a little big, 5V current inputed is better not to be as low as 3A。
![]()
PCBSATA信號上面串聯的4個電容要緊挨SATA座。
the four capacitors which are serialed to SATA signal should be close to SATA booth。
100歐姆的差分阻抗匹配
100 ohm difference resistance matching up
每組差分對之間的長度誤差控制在±5mil
length tolerance for each group of differences pairs is controlled within ±5mil
要求完整參考地平面
require a full reference to ground level
HDMI
原理(principle)HDMI座子不能夠接錯定義
HDMI stand can't be linked with wrong definition
![]()
PCB100歐姆差分阻抗匹配。
100 ohm difference resistance matching up。
每組差分對之間的長度誤差控制在±5mil
length tolerance for each group of differences pairs is controlled within±5mil
要求完整參考地平面
require a full reference to ground level
保護器件CM2020一定不要省略。
protect component CM2020 can't be ignored。
LVDS
原理(principle)LVDS信號如果傳輸距離比較遠，接的屏幕比較大，LVDS信號上面可以串聯耦合磁珠，能夠保證傳輸的質量更好。
if transmitting distance for LVDS signal is long，and screen linked with is big接的屏幕比較大，amagnetic coupling can be put in serial on LVDS signal for a better transmiting quality。
PCB100歐姆的差分阻抗匹配。
100 ohm difference resistance matching up。
每組差分對之間的長度誤差控制在±5mil
length tolerance for each group of differences pairs is controlled within±5mil
如果用雙路LVDS信號做1080p的顯示。LVDS0跟LVDS1的信號要做等長處理。
if two way LVDS singla is used for 1080p displa,。LVDS0 and LVDS1 signal need an equal treatment。
要求完整參考地平面
require a full reference to ground level
RGB接口LCD(RGB port LCD)
原理(principle)RGB接口的LCD滿足24bit，18bit的接口模式
LCD as RGB port need to be matched up with interface model with 24bit，18bit
CPU信號（注1）
(CPU signal（note1）) | 24bit（注2）
(24bit（note2）) | 18bit（注3）
(18bit（note3）) | 18bit（注4）
(18bit(note4)) | | D0 | B0 | | B0 | | D1 | B1 | | B1 | | D2 | B2 | B0 | B2 | | D3 | B3 | B1 | B3 | | D4 | B4 | B2 | B4 | | D5 | B5 | B3 | B5 | | D6 | B6 | B4 | G0 | | D7 | B7 | B5 | G1 | | D8 | G0 | | G2 | | D9 | G1 | | G3 | | D10 | G2 | G0 | G4 | | D11 | G3 | G1 | G5 | | D12 | G4 | G2 | R0 | | D13 | G5 | G3 | R1 | | D14 | G6 | G4 | R2 | | D15 | G7 | G5 | R3 | | D16 | R0 | | R4 | | D17 | R1 | | R5 | | D18 | R2 | R0 | | | D19 | R3 | R1 | | | D20 | R4 | R2 | | | D21 | R5 | R3 | | | D22 | R6 | R4 | | | D23 | R7 | R5 | |
注1(note1).
D0表示CPU的液晶接口最低位，
D0 indicate a minimal level for CPU liquid crystal port，
D23表示CPU的液晶接口最高位
D23 indicate a maximal level for CPU liquid crystal port
注2(note2)
B0-24位液晶藍色位最低位，
B0-24 bit blue bit of liquid crystal at minimal level，
B7-24位液晶藍色位最高位
B7-24 bit blue bit of liquid crystal at maximal level,
G0-24位液晶綠色位最低位，
G0-24 bit green bit of liquid crystal at minimal level，
G7-24位液晶綠色位最高位
G7-24 bit green bit of liquid crystal at maximal level
R0-24位液晶紅色位最低位，
R0-24 bit red bit of liquid crystal at minimal level，
R7-24位液晶紅色位最高位
R7-24 bit red bit of liquid crystal at maximal level
注3(note3).
采用此接法，LCD軟件還是選用24bit模式
in use of this kind of link，LCD software still choose 24bit model
B0-18位液晶藍色位最低位，
B0-18 bit blue bit of liquid crystal at minimal level，
B5-18位液晶藍色位最高位
B5-18 bit blue bit of liquid crystal at maximal level
G0-18位液晶綠色位最低位，
G0-18 bit green bit of liquid crystal at minimal level，
G5-18位液晶綠色位最高位
G5-18 bit green bit of liquid crystal at maximal level
R0-18位液晶紅色位最低位，
R0-18 bit red bit of liquid crystal at minimal level，
R5-18位液晶紅色位最高位
R5-18 bit red bit of liquid crystal at maximal level
注4(note 4).
采用此接法，LCD軟件要改成選用18bit模式
if in use of this link method，LCD software need to choose 18bit model
B0-18位液晶藍色位最低位，
B0-18 bit blue bit of liquid crystal at minimal level，
B5-18位液晶藍色位最高位
B5-18 bit blue bit of liquid crystal at maximal level
G0-18位液晶綠色位最低位，
G0-18 bit green bit of liquid crystal at minimal level，
G5-18位液晶綠色位最高位
G5-18 bit green bit of liquid crystal at maximal level
R0-18位液晶紅色位最低位，
R0-18 bit red bit of liquid crystal at minimal level，
R5-18位液晶紅色位最高位
R5-18 bit red bit of liquid crystal at maximal level
如果靜電要求非常嚴格，LCD信號上面要做ESD防護。
if there is a strict request with static，need ESD protect for LCD signal。
PCB所有的數據線，CLK信號要做等長處理
for all data lines，need an equal treatment for CLK signal
要求完整參考地平面
request a full reference to ground level
CMOS
原理(principle)PCBMCLK和PIXCLK信號頻率非常高，Layout時要做地隔離處理
since frequency of MCLK and PIXCLK signal is very high，need isolation treatment when Layout
數據，clk信號要做等長處理。
data，need an equal treatment for clk signal。
要求完整參考地平面
request a full reference to ground level
USB
原理(principle)USBHOST通過LAN9514擴展了4和USBHOST，同時擴展了1路10M/100M的以太網接口。
USBHOST expanded with 4 and USBHOST via LAN9514，and expanded with one way 10M/100M ethernet interface。
USB線上串耦合電感。
a coupling inductance is put in serial on USB line。
核心板的USB_H1_VBUS信號要通過磁珠接5V電源。
核心板的USB_H1_VBUS signal of coure board need to be connected with 5V power supply through magnetic bead。
對外做HOST供電時，要采用USB過流保護器件。
if power supply Host out of the board,please include over-current protect component for USD。
![]()
目前的MINIUSB口硬件設計上只能夠做device口，如果要做HOST功能，請參考FSL官方的OTG設計即可。
so far only device port can be done in layout of hardware for MINIUSB port，if need function of HOST，please refer to OTG layout from FSL official。
90歐姆的差分阻抗匹配
90 ohm difference resistance matching up
要求完整參考地平面
request a full reference to ground level
對外供電的電流足夠大。
current to supply outside need to be big enough。
CAN
原理(principle)由于CAN的TX,RX信號是3.3V電平，注意電平轉換。
since CAN的TX,RX signal is 3.3V electrical level，attention to conversion of electrical level。
![]()
PCBCANH,CANL查分信號。
CANH,CANL check signal。
PCIE
原理(principle)TX,RX信號要串聯0.1uF電容（外接模塊上面如果RX信號已經串聯了電容，不需要再次串聯）
TX,RX signal need to connect in serial with 0.1uF capacitor（if an external module is already with a capacitor in serial,then no need to connect a capacitor again）
CLK信號上串聯0.1uF電容，同時在電容后端并聯一個49.9歐姆的對地電阻。
CLK signal connect in serial with 0.1uF capacitor,at the same time put a 49.8 resistor to ground in parallel with another end of the capacitor 。
![]()
PCB85歐姆的差分阻抗匹配
85 ohm difference resistance matching up
要求完整參考地平面
request a full reference to ground level
| 
發表于 2018-3-16 13:53:20
收藏
頂
踩