|
NO.73-【獵頭職位：上海需要一位 Memory Modeling Portfolio engineer存儲設計】聯系人：Shinely-Li,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ PositionDescription: Ø Responsible for scheduling,designing, developing, and supporting IP models of system level memory such asSDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFSmodels for use on hardware based verification products. Also responsible forupdating, maintaining, documenting, and supporting existing system level memorymodel products. Perform as individual contributor for RTL design, verification,productizing, and documentation of memory IP. Position Requirements: Ø The position requires BSEE, orequivalent, with a minimum of 4 years of industry experience in designinghardware systems. RTL design knowledge using Verilog/System Verilog is requiredalong with experience using RTL verification tools and flows. Debugging experience.Experience with team-wide collaboration tools and process. 福利：美資13薪+bonus+五險公司繳納+股票 |
