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【獵頭職位：成都需要一位 Verification Team Leader】聯系人：Judy-Wu，郵箱：hr@kthr.com，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Responsibility: Write the verification plan according to the Chip/IP specification； Setup the whole verification environment with the advanced verification methodologies； Design the behavioral functional model with Verilog/System Verilog, C/System C； Create the direct test pattern and constrained random test pattern to test the DUT； Work closely with RTL designer to assist in simulation debug/code coverage analysis. Qualification: Master/Bachelor degree on Electrical/Electronics, Computer Engineering or C-ommunication； Minimum of five years experiences on IC Design/verification/emulation experiences； Experience on VMM/OVM/UVM and knowledge of VIP are preferred； Familiar with Perl/Python, shell programming and excel operation is a plus .Expert knowledge of C/C++/SystemC ,VHDL/Verilog HDL, HVL(systemverilog) and simulation tools； Able to setup the verification environment and verification flow independently； Basic knowledge of logic and circuit design, knowledge of microprocessors and computer system architecture is a plus； Proactively learner and eager for new technologies； Excellent interpersonal and communication skills, good teamwork adaptability, good written English skills, self-motivated. |
