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【獵頭職位：上海需要一位 SOC/HW-VLSI/Validation SDC】聯(lián)系人：Grace-Tai，郵箱：hr@kthr.com，微信也可查詢職位啦！打開手機(jī)微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Responsibilities： -Interfacing with the design teams toensure DFT design rules and guidelines are met； -Verification of ATPG test patterns for(SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models； -MBIST verification and test patterngeneration through Mentor tool； -Work closely with design team on IDDQconstrains validation； --Work with design team on functional DFTtest pattern generation and simulation； -Simulating and verifying the ATPG (SAF, TDF)and MBIST patterns on unit delay and min/max timing corners； -Work with QVPS team on the test vectorsimulation and delivery； -Work with Test Engineers to debug/diagnosemanufacturing defects； -Maintain existing DFT verificationenvironments； -Developing, enhancing and maintainingscripts as necessary； Basic Qualifications: Required: 5+ years ASIC/DFT and various aspectssimulation, Silicon validation or similar education/experience equivalent； Preferred: -Detailed knowledge on DFT concepts,pattern simulation, Silicon debug； -JTAG, MBIST, Scan Compression, ATPG, FaultSimulation and at-speed testing； -Rich experience with gate level simulation； -Rich experience with UVM； -Excellent problem solving skills； -Experience with one or more scriptinglanguages(Perl/TCL) is desired； -Strong written and verbal communicationskills； Education Requirements BS/MS degree in Electrical Engineering,Computer Science, or related field 
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