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【獵頭職位：上海需要一位“Sr. staff verification engineer”】關鍵詞：UVM, verification,聯系人：Susan，QQ:15902188625；Skype:susan.lu63；Email: susan-lu@kthr.com，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Job Description 1.Define verification infrastructure using System Verilog, Formal and UVM. 2.Assist in complete verification of high performance, high feature, low power ASIC. 3.Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure. 4.Guide the development of comprehensive, flexible, and portable block to chiplevel test-benches, detail test plans and coverage closure. 5.Expert in industry standards such as PCIe, USB, Ethernet, 802.3, 802.11, ARM, etc. 6.nfrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements. Job Requirements 1.Strong verification and technical lead skills including a good knowledge and understanding of different verification methodologies: * architecture vs micro-architecture level * random vs directed testing * fullchipvs module-level * performance vs function * error & drop handling 2.Past experience of successfully technically guiding complex, multi-million gates, high speed design verification. 3.Experience with the following areas in design and verification: * Advanced Constrained-random functional verification methodology such as OVM/UVM/VMM and/or SV Assertion. * Systems using communication systems/protocols such as 802.3, PCIe, USB3, AXI, 802.11, ARM and NoC. * Formal verification with abstraction model for end-to-end checking. * Low power verification with power gating and power management. * Debug methodology 4.Self-motivated, good communicator, quick learner and good team player. 5.Display positive attitude and demonstrate flexibility in day-to-day work. 6.MS/EE or CS with 12-16 years of relevant experience. 
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