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1.【獵頭職位：上海需要一位“ASIC Digital Design Engineer”】關鍵詞：ASIC Digital Design，聯系人：Lily，MSN:anaelily@gmail.com,Email: lily-zhuang@kthr.com,weibo:weibo.com/anaelily，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Responsibilities: l.Responsible for logic design and verification in low-power wireless communications chips. 2.Also responsible for module-level lint checking, timing checking and formal verification. Qualifications: l.Proficiency in logic design, simulation, synthesis and testing. 2.Proficiency in Verilog and its simulation environment. 3.Experience with low-power design. 4.Good knowledge of SOC design. 5.Experience in wireless communication or multimedia technologies is a plus. 5.Experience in ARM and AMBA design is a plus. 5.Self-motivated and good team player. 6.MSEE or BSEE with 2+ years. 2.【獵頭職位：上海需要一位“ASIC Digital Verification Engineer”】關鍵詞：LTE DSP Firmware 物理層，聯系人：Lily，MSN:anaelily@gmail.com,Email: lily-zhuang@kthr.com,weibo:weibo.com/anaelily，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關注！ Responsibilities: l.Make verification plan for one module or whole chip. 2.Build up and maintain module-level and chip-level verification environment 3.Verify ASIC digital design based on case list, and output verification report. 4.Also responsible for lint checking and formal verification. Qualifications: l.Proficiency in logic verification. 2.Experience with Verilog logic design language. 3.Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language. 4.Experience with UNIX/Linux simulation tools such as IUS or VCS. 5.Experience with C and C++ is a plus. 6.Experience with C_SHELL, TCL or PERL is a plus. 7.Experience with UVM, OVM or VMM is a plus. 8.Good knowledge of SOC design is a plus. 9.Good knowledge of software design is a plus. 10.Self-motivated and good team player. l1.MSEE or BSEE with 2+ years. |
