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標(biāo)題: 請(qǐng)問(wèn) 我的ISE工程生成了TESTBENCH文件用modelsim仿真的時(shí)候只能出來(lái)一個(gè)周期 [打印本頁(yè)]

作者: lazy17362012 時(shí)間: 2017-11-13 20:44
標(biāo)題: 請(qǐng)問(wèn) 我的ISE工程生成了TESTBENCH文件用modelsim仿真的時(shí)候只能出來(lái)一個(gè)周期
我ISE的工程生成了TESTBENCH文件用modelsim仿真的時(shí)候只能出來(lái)一個(gè)周期不知道是代碼的問(wèn)題還是設(shè)置的問(wèn)題下面附上工程代碼和tb代碼
library ieee;
use ieee.std_logic_1164.all;
entity div10 is
   generic(n:integer :=10);
   port (clk:in std_logic;
            q

ut std_logic);
end div10;
architecture behave of div10 is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
      if (clk'event and clk='1' and clk'last_value ='0') then
      count<=count-1;
         if count>= n/2 then
            q<='0';
         else
            q<='1';
         end if;
         if count<=0 then
            count<=n-1;
         end if;
      end if;
   end process;
end behave;

ENTITY tb_div10 IS
END tb_div10;

ARCHITECTURE behavior OF tb_div10 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT div10
PORT(
      clk : IN  std_logic;
      q : OUT  std_logic
      );
END COMPONENT;

--Inputs
signal clk : std_logic := '0';

--Outputs
signal q : std_logic;

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: div10 PORT MAP (
      clk => clk,
      q => q
      );

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
   -- hold reset state for 100 ns.
   wait for 100 ns;

   wait for clk_period*10;

   -- insert stimulus here

   wait;
end process;

END;

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